1. Field of the Invention
The present invention relates generally to a mask design and, in particular to the logic optimization and synthesis of that design based on cost.
2. Related Art
As integrated circuits become increasingly complex, engineers are increasingly using electronic design automation (EDA) tools, such as logic synthesis tools, to convert architectural designs, which describe desired circuits and their interconnection on an integrated circuit, into mask layouts. FIG. 1 illustrates a conventional logic synthesis process 100. In process 100, an architectural design 101, which describes features of the integrated circuit, can be provided. This architectural design 101 can be written in a Hardware Description Language (HDL), such as VHDL or Verilog. In step 102, a compiler tool can perform a logic synthesis (also called a compile) of architectural design 101. To perform this function, the compiler receives architectural design 101 as well as information from a cell library 106 and one or more constraints 107.
Cell library 106 contains detailed information regarding the cells of the specific proprietary technology selected (e.g. from LSI, VLSI, Texas Instruments, Xilinx Inc., etc.). Such information could include, for example, a description of the logic, area, timing, power consumption, and pin descriptions, for each cell in cell library 106. Note that cells in cell library 106 can include various levels of complexity. For example, cells can provide models of specific transistors, logic gates (AND, OR, XOR etc.), or even functional units (e.g. adders, multiplexers, etc.).
Constraints 107 can be used to weigh certain parameters to ensure desired characteristics of the resulting integrated circuit. These desired characteristics could relate to, for example, area, timing, testability, power consumption, and other physical limitations associated with the integrated circuit. In logic synthesis (step 102), the compiler can map architectural design 101 onto cell library 106 while trying to achieve constraints 107. At this point, a preliminary netlist can be generated.
In step 103, the compiler can then perform physical processing on the preliminary netlist. This physical processing includes determining the optimal placement of components in the design. In one embodiment, this physical processing can include partitioning, floor planning, placement, routing, and compaction. The objective of physical processing is to generate the most efficient mapping of the components in the integrated circuit.
In step 104, the resulting mapped netlist can be checked to verify its performance. This verification can be performed using layout versus schematic (LVS), design rule checking (DRC), or layout extraction tools. In step 105, an output file including the mapped netlist can be generated. At this point, the mapped netlist can be used to fabricate a mask set for exposing a wafer that will provide the desired integrated circuit.
A typical mask set for a technology node above 0.13μ has typically averaged about $30,000. Because such mask set cost was roughly only 2% of the total chip fabrication cost, this metric was not as important a factor as the standard metrics of timing, area, and power. Unfortunately, mask set cost has dramatically increased due to demand for even smaller device sizes as well as chip complexity. For example, a current mask set for technology below 0.13μ could now cost $800,000 to $1,000,000, which comprises about 10% of the total chip cost.
Therefore, a need arises for a technique of incorporating consideration of mask cost into a logic synthesis process.